My Dev board gave up on me
Integrated multiple peripherals and learnt new concepts
FPS Drop Issue
So since the last post i was mentioning that i had a FPS Drop issue, where i tried stablizing with and without the DMA2D to 35 FPS, but i was reading more on how to increase the fps and ended up studying the CACHE for the first time i read through the an4839 (From STM32), this is a manual for both cortex M7, F7, H7 series MCU's, read through it then i understood how cache is very important for an mcu to boost its performance, and reduce repetative taks, the ARM M7 core had L1 Cache, it had for both I cache and D cache, both were size of 16KB, Also i learnt 4 funtions
- Cache Enable
- Cache Disable
- Cache Clean
- Cache Invalidate
I Cache
then first i tried turning on the I Cache, after a few failed attempts i finally turned on the the I Cache, and it improved the fps asap, it went from 35 fps to 50+ fps. But still the huge load of data was moving from the ext sram to the display, making the load very high like 80%.
D Cache
So the next step was to enable the D Cache, after enabling it i coundnt believe, the fps went to 60+ and the load reduced to 13%, i was so stunned.
My First GUI Using LVGL
Before enabling the caches, i was trying to make my own gui for the first time using the lvgl without any help, so i went to the lvgl simulator in the my desktop, and tried to making an rgb color mixer, basically the idea was to have three sliders ranging from 0-255 (8 bits) each, and a rectangular box where i show the color acc to the rgb value of the slider. I tried making one in the simulator there was no issues, like there was no fps drop. and when i managed to implement the same gui in my stm32 the whole gui froze, it was an disater, also i did not know there was something known as even_CB in the lvgl, its like a interrupt, so then figured that out and this time i was not completely froze but the cpu load was like 90% and fps was still struggling, so then i read about caches and eventually, fixed this issue for now, using both the I & D Cache, now it works smoothly.
Square Line Studio and PWM Brightness Control
Next i randomly found this tool called, square line studio where we can make embedded based gui's using LVGL, so i was trying to explore that, since i also had a requirement to control the brightness of the display i am using now with pwm, so i though of making a simple slider with event_cb, and ended up making an gui for that, and implement into a folder of my project, and it generated and i was so easy to use and intialized the function provide by the squareline gui files, after that i created a new file for timers, and implement pwm in 1KHz, and implemeted in the event_cb function, and it worked perfectly.
SDMMC and FATFS
Next i also implemented the the SDMMC for micro SD Card, in 4 Bus Width Mode, fo the file handling i useed the FATFS Library from the STM32's Middleware, and with lots of bugs and errors, finally made it work. Create a text file.
The MCU Gave Up
Yesterday i was actually testing the I2S, for enabling it for the ble as well, so i was trying to compile the code and flash it all of a sudden in between the stlink throwed an error and stopped working, and the leds in the board did not turn on i removed everything and i tried doing a CPR to the board by removing the regulator still no success, and when when plugged on with the type c cable the mcu was getting really hot, also i was checking the conductivity in between the 3.3v and gnd, it was beeping, so thats all the mcu gave up on me. and when i tried plugging on the st link module, it was also not working. Yup i had to re order the MCU.
Studying the AMBA Architecture
In the mean time i started studying about the AMBA Architecture i learnt a lot, ,
AMBA intro
AMBA stands for Advanced microcontroller Bus Architecture.
- open standard.
- on-chip interconnect specification.
- Defines the connection and management of functional blocks in system on chips (SoCs).
AMBA is a standard for ARM cores/SoCs
Bus interface performance
Two main characteristics of interface performance are:
- Bandwidth - Rate of data across the interface.
- The maximum bandwidth is limited by the product of the clock speed and the width of data bus.
- Aim = use the max Bandwidth available.
- Latency - Delay btw start and end of the transaction.
- Aim = zero latency
Evolution of ARM AMBA spec
AMBA-1 (1997)
APB -> 1997 -> Advanced peripheral Bus
- Low Bandwidth
- Has an address & a place to store data.
AMBA-2 (1999)
AHB -> 1999 -> Advanced High Performance Bus
- a single clock has address phase & a data phase
- large bus width than APB
AP2 -> 1999
AMBA-3 (2003)
AP3 ->
AHB-lite -> Subset of AHB
ATB -> Advanced Trace Bus
- part of arm coresight (debug & trace)
AXI3 -> Advanced extensible Interface
- High performance
- High clock frequency system.
AMBA-4 (2010-11)
APB4 ->
ACE -> AXI Coherency Extensions
- ACE extends AXI with additional signaling introducing system-wide coherency
- This system coherency allows multiple processors to share memory and enable technology like arm's big little processing.
- It also enables one-way coherency eg,
AXI4 -> uni directional data transfer from master to slave known as point to point with reduced signal routing
AMBA5 (2013-2017)
CHI -> Coherent Hub Interface.
- High speed transport layer, reduce congestion
DTI - Distribution Translational interface.
ATP - Adaptive traffic profiles.
AXI Protocol
AXI Protocol Structure
AXI master
ā
AXI interconnect components
ā
AXI Slave
AXI Features
AXI has 2 Channels
- one for read
- another for write
multiple out standing addresses.
- This means master can issue transactions without for earlier transaction to complete.
- This improves system performance, because it enables parallel processing of transactions.
no strict timing relationship b/w the addressand data phases.
AXI also supports for unaligned data transfers.
Out of order-transaction completion.
Burst transactions based on start address issue only
AXI Channels
Write
- write Address (AW) ->
- write Data (W) ->
- write Response (B) <-
Read
- Read address (AR) ->
- Read Data (R) <-
All the channels are uni directional.
AHB Protocol
For the AHB protocol i was reading the (IHI0033C) manual.
AHB:
It is the interaction btw 3 components:
- Managers(masters): Initiate transactions by issuing read & write commands.
- Subordinates(slaves): Respond to Manager requests and provide or store data.
- Interconnects: Handle data routing & arbitration b/w managers and subordinates.
It has Single clock-edge operation: It operates synchronously on the rising edge of a clock, ensuring predictable timing.
Burst transfers: AHB supports single and burst transfers, improving data throughputs.
What I did
- Studied and implemented lots of peripherlas like Cache and Sd Card
Next
- Since the Dev board will take time to arrive, i am currently studying DMA, and more about the pheriphrals in the core and the architecture.
- Start working on the actual gui and the emulator, and also i am thinking of porting the whole poject into rust, also writing my own OS, from Scratch, and integrate everything with the rust, i am not sure though, need to study more about how an game emulator works, need to look into the gameboy emulator.