Cortex-A9 Bare-Metal DSP System

This project is broader than a small platform experiment. It is a complete bare-metal DSP system built on the DE1-SoC platform around the ARM Cortex-A9 inside the Cyclone V SoC.

The README makes the focus clear: low-level hardware ownership, real DSP pipelines, external-device control, and measurable optimization using ARM NEON SIMD intrinsics. The system runs without an operating system and uses direct register access to HPS peripherals, FPGA-mapped IP, storage, sensors, audio output, UART transport, and LCD display.

What the system does

The project supports several end-to-end processing paths inside one runtime:

• audio FIR filtering and playback through the WM8731 codec
• SDR FIR and FFT-domain filtering on I/Q sample data
• ADXL345 accelerometer smoothing with a Kalman filter
• median filtering for BMP image data
• UART export of raw and filtered DSP results
• LT24 LCD output for raw and filtered image display

What makes it strong as a portfolio project is that these are not isolated demos. The switches, LEDs, HEX displays, UART host protocol, audio path, display path, and processing modules are all tied together into one embedded software stack.

Architecture and implementation depth

The implementation spans multiple layers:

• core runtime support with GIC, IRQ dispatch, timer tick, and cache maintenance
• HPS peripheral drivers for UART, I2C, GPIO, clock, reset, watchdog, and SDMMC
• FPGA lightweight bridge access for switches, LEDs, keys, HEX displays, audio FIFO, and LCD GPIO
• external-device support for the ADXL345, WM8731, and LT24
• file parsing and media handling using FatFs
• DSP pipelines built in scalar C first and then optimized with ARM NEON

This is the part that makes it different from a typical MCU project. It is not only about drivers or only about algorithms. It is about integrating SoC-level hardware control with real compute-heavy processing and then proving the gains with benchmarking.

Performance results

The benchmark section in the README gives the project strong evidence:

• audio FIR: 190 ms scalar to 30 ms NEON, about 6.33x
• SDR FIR: 25 ms scalar to 5 ms NEON, 5x
• SDR FFT: 671 ms scalar to 140 ms NEON, and 72 ms with LUT support

That makes the project valuable not just as a bare-metal bring-up exercise, but as a measured performance-engineering project.

What it says about me

This project shows that I can work across low-level initialization, hardware interfacing, DSP implementation, verification, and optimization in one system. It also shows that I am comfortable working in environments that are larger and rougher than a standard microcontroller setup, where platform structure and performance both matter.