SMSSrivisweswara Mohan SanthiEmbedded Software/Firmware Engineer
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2026

High Frequency Trading Verifier

A module project for FPGA Design for System-on-Chip, focused on hardware-side trade validation logic for low-latency checking and deterministic decision flow.

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High Frequency Trading Verifier project image.
Module Project / 2026Project overview

Visual from the FPGA Design for System-on-Chip module project on hardware-assisted trade verification.

Highlights

  • Designing hardware-side checks for price ranges, quantity thresholds, and sanity validation.
  • Exploring how FPGA parallelism can reduce latency for pre-trade verification logic.
  • Translating a finance-domain safety problem into deterministic hardware behavior.
  • Extending embedded thinking beyond classical MCU-only work.

This project came from the FPGA Design for System-on-Chip module in my master's course rather than from my final MSc dissertation. I used it to explore how FPGA-style thinking can be applied to a finance-domain verification problem.

The idea behind the project was to build a high frequency trading verifier that could pre-check trade parameters before execution. Instead of relying only on software-side validation, the concept pushes selected sanity checks into hardware so invalid or suspicious trade requests can be filtered earlier with deterministic behavior and lower latency.

The implementation work was built around the DE1-SoC platform and focused on how FPGA fabric can be used for parallel, hardware-level validation. That made it a good fit for exploring low-latency checking, hardware-software partitioning, and the broader design mindset behind safe real-time systems.

What I like about this project is that it shows my embedded interest is not tied to one application domain. The same instincts still apply: push critical checks earlier, make systems more deterministic, and use hardware where it gives a real architectural advantage.